In the semiconductor industy, strong efforts are made to bring a new promising memory technology based on non-volatile MRAM cells into practical use. An MRAM cell includes a stacked structure of magnetic layers separated by a non-magnetic tunneling barrier layer or conductive barrier. Using a non-magnetic tunneling barrier layer, a magnetoresistive tunnel junction (MTJ) memory cell is formed. Using a conductive barrier, a giantmagnetoresistive memory cell is formed. Here, and in agreement with conventional reading in the art, both alternatives are included by the term “magnetoresistive memory cell”.
In MRAM cells, digital information is not maintained by power, as in conventional DRAMs, but rather by directions of magnetizations in the ferromagnetic layers. More specifically, in an MRAM cell, magnetization of one ferromagnetic layer (“reference layer” or “pinned layer”) is magnetically fixed or pinned, while magnetization of the other ferromagnetic layer (“free layer”) can be switched between two preferred directions along an easy axis of magnetization thereof, which typically is in parallel alignment with the reference layer fixed magnetization.
Depending upon the magnetic orientation of the free layer, an MRAM cell exhibits two different resistance values in response to a voltage applied across the MRAM cell, wherein the resistance thereof is “low” when magnetizations are in parallel alignment and “high” when magnetizations are in antiparallel alignment. Accordingly, logic values (“0” and “1”) may be assigned to different magnetizations of the free layer and detection of electric resistance allows to provide the logic information stored in the magnetic memory element. An MRAM cell typically is written to by applying magnetic fields created by bi- or unidirectional currents made to run through conductive lines operatively located adjacent the MRAM cell so that magnetic fields thereof are coupled to the free layer magnetization.
In view of modern portable equipment, such as portable computers, digital still cameras, and the like, that require very large memory performance, one of the most important issues for memory devices is a further down-sizing thereof to allow an increased memory cell density. To this end, the stored number of bits per memory cell is increased by using a multibit memory cell architecture in which each memory cell includes a plurality (typically two) of series-connected magnetoresistive tunnel junctions (MTJs) per single access transistor. In such architecture, magnetoresistive tunnel junctions of one memory cell typically have different magnetoresistivities, i.e., different resistance values in response to a voltage applied across each magnetoresistive tunnel junction. Since a single access transistor is used for selecting plural magnetic memory elements and for a read operation thereof, integration density may be enhanced compared to other architectures comprising only one magnetoresistive tunnel junction per single access transistor. In above multibit memory cell architecture, in order to achieve a strong magnetic coupling of conductive lines to each of the MTJs, each MTJ typically is located in an intermediate position of adjacent conductive lines. Hence, in order to connect plural MTJs of a single memory cell and due to lateral dimensions of conductive lines, electric interconnects have to bypass conductive lines positioned in between MTJs to be connected, which by-passing, however, is detrimental in terms of achieving a high integration density of the memory device.
In light of the above, it is an object of the invention to provide a magnetoresistive memory cell allowing to improve integration density in memory devices particularly with regard to multibit memory cell architectures.